1. Field of the Invention
The present invention relates to a method for driving an AC-type plasma display panel and a plasma display device.
The present application claims priority of Japanese Patent Application No. 2002-366675 filed on Dec. 18, 2002, which is hereby incorporated by reference.
2. Description of the Related Art
Generally, a plasma display panel (hereinafter simply called a PDP) has many features that it is capable of being made thin, a large-screen display, providing a wide viewing angle, and giving a fast response (see Patent References 1 to 15 as be described later).
Therefore, in recent years, a PDP is used as a flat display device for a wall-hung television set, a public display board, or a like. A plasma display device using a PDP is classified, depending on its driving method, into two, one being a Direct Current discharge type of plasma display device (hereinafter referred to as DC-type plasma display device) and another being an Alternating Current discharge type of plasma display device (hereinafter referred to as AC-type plasma display device). In the DC-type plasma display device, electrodes are exposed in discharge space (discharge gas) and drive a PDP in a state where DC discharge occurs. In the AC-type plasma display device, an electrode is covered with a dielectric layer, not disposed directly in discharge gas and drives a PDP in a state where AC discharge occurs. In the DC-type plasma display device, discharge occurs in all periods during which a voltage is being applied to an electrode. In the AC-type plasma display device, discharge is sustained by reversing a polarity of a voltage to be applied to an electrode. Moreover, the AC-type plasma display device can be classified into two, one in which the number of electrodes formed in a cell is two and another in which the number of electrodes formed in a cell is three.
Now, a plasma display device using a three-electrode AC-type PDP as a plasma display device being applied to a conventional method for driving the conventional PDP is described.
FIG. 17 is a diagram showing schematically configurations of a conventional plasma display device (plan view of a conventional three-electrode AC-type PDP) . The conventional plasma display device, as shown in FIG. 17, includes a display screen 130, m-pieces of scanning electrodes 122 (scanning electrodes 122-1 to 122-m, where “m” is a positive integer greater than one), m-pieces of sustaining electrodes 123 (sustaining electrodes 123-1 to 123-m), n-pieces of data electrodes 129 (data electrodes 129-1 to 129-n, where “n” is a positive integer greater than one), and (m×n) pieces of display cells 131. The (m×n) pieces of the display cells 131 are arranged in m-rows and n-columns. In each of n-pieces of display cells belonging to one row out of m-rows, the scanning electrode 122-i (i=1, 2, . . . , m) and the sustaining electrode 123-i (i=1, 2, . . . , m) are formed in parallel to each other. In each of m-pieces of the display cells 131 belonging to one column out of n-columns, the data electrode 129-j (j=1, 2, . . . , n) is formed in a manner so as to be orthogonal to both the scanning electrode 122-i and the sustaining electrode 123-i. Between the scanning electrode 122-i and the sustaining electrode 123-i is provided a discharge gap 134 with a first interval between them. Between the scanning electrode 122-i and the sustaining electrode 123-(i−1) and between the scanning electrode 122-(i+1) and the sustaining electrode 123-i, a non-discharge gap 135 is provided with a second interval between them.
To the conventional plasma display device is connected a driving control circuit 138 as shown in FIG. 17. The driving control circuit 138 includes a driving section 136 and a controlling section 137. The driving section 136 has a scanning driver (not shown), a sustaining driver (not shown), and a data driver (not shown). The scanning driver is connected to the scanning electrodes 122-1 to 122-m, the sustaining driver is connected to the sustaining electrodes 123-1 to 123-m, and the data driver is connected to the data electrodes 129-1 to 129-n. One terminal of the controlling section 137 is connected to a ground and another terminal of the controlling section 137 is connected to the driving section 136. The controlling section 137 drives the driving section 136 so that a potential described later is applied through the scanning driver, sustaining driver, data driver to the scanning electrodes 122-1 to 122-m, sustaining electrodes 123-1 to 123-m, and data electrodes 129-1 to 129-n. Here, a difference in an electric potential between two electrodes, between an electrode and the driving control circuit 138 or a like, as known well, is called a “voltage” or a “potential difference”.
FIG. 18 is a cross-sectional view of one of display cells making up the conventional thee-electrode AC-type PDP as shown in FIG. 17. The conventional thee-electrode AC-type PDP, as shown in FIG. 18, further includes an upper insulating substrate (front substrate) 120, a lower insulating substrate (rear substrate) 121, a transparent dielectric layer 124, a protecting layer 125, a phosphor layer 127, a white dielectric layer 128, and metal trace electrodes 132. The front substrate 120 and the rear substrate 121 face each other. The front substrate 120 and the rear substrate 121 are made up of, for example, a glass substrate.
Between the front substrate 120 and the rear substrate 121, that is, on the front substrate 120, the scanning electrode 122-i and the sustaining electrode 123-i are mounted, with the first interval between them and in parallel to each other. The first interval is the discharge gap 134. Among the scanning electrode 122-i, the sustaining electrode 123-i, and the rear substrate 121, that is, on the scanning electrode 122-i and sustaining electrode 123-i, the metal trace electrodes 132 used to reduce wiring resistance are formed. Among the front substrate 120, the scanning electrode 122-i, the sustaining electrode 123-i, metal trace electrode 132, that is, on the front substrate 120, the scanning electrode 122-i, the sustaining electrode 123-i, and the metal trace electrode 132, the transparent dielectric layer 124 is formed. Between the transparent dielectric layer 124 and the rear substrate 121, that is, on the transparent dielectric layer 124, the protecting layer 125 used to protect the transparent dielectric layer 124 from damages caused by discharge is formed. The protecting layer 125 is made of, for example, MgO (Magnesium Oxide).
Between the protecting layer 125 and the rear substrate 121, that is, on the rear substrate 121, a data electrode 129-j is formed in a manner so as to be orthogonal to both the scanning electrode 122-i and the sustaining electrode 123-i. Between the protecting layer 125 and the data electrode 129-j, that is, on the data electrode 129-j, the white dielectric layer 128 is formed. Between the protecting layer 125 and the white dielectric layer 128, a first phosphor layer 127-1 and a second phosphor layer 127-2 are formed as the phosphor layer 127. That is, on the white phosphor layer 128 is formed the first phosphor layer 127-1. On the first phosphor layer 127-1, the second phosphor layer 127-2 extending from both sides of the first phosphor layer 127-1 to the protecting layer 125 in a vertically upward direction of the first phosphor layer 127-1 so that a discharge space 126 is formed. Between the front substrate 120 and the rear substrate 121, a non-discharge space 133 is formed in a manner that each display cell 131 is surrounded by end portions of the second phosphor layer 127-2 and first phosphor layer 127-1, the protecting layer 125, and the white dielectric layer 128. The second phosphor layer 127-2 serves as a rib (partition wall). The rib (second phosphor layer 127-2) plays a roll in securing the discharge space 126 and in partitioning a pixel (display cell 131). The discharge space 126 is filled with a discharging gas, such as a mixed gas of He (helium), Ne (neon), Xe (xenon).
Next, the method for driving the conventional plasma display device (conventional PDP) is described. A method for driving the plasma display device being presently in the mainstream is a scanning and sustaining separating method, that is, a method called an “ADS” (Address and Display Separation) method in which a scanning period is separated from a sustaining period. Hereinafter, the ADS method is explained. FIG. 19 is a timing chart showing waveforms of voltages applied for driving the conventional plasma display device.
As shown in FIG. 19, one sub-field 105 (hereafter simply referred to as a “sub-field” 105) includes an initializing period 102, a scanning period 103, and a sustaining period 104. The initializing period 102 is a period during which wall charges having been accumulated between the scanning electrode 122-i and the sustaining electrode 123-i when sustaining discharge occurred during the sustaining period are erased (initialized or reset), to which timing P106, P107, P108, P109, P110, P111, P112, and P113 following timing P101 corresponds. The scanning period 103 is a period during which video data to display a video is written in an address (display cell 131) by causing writing discharge to occur between the scanning electrode 122-i and data electrode 129-j, to which the timing P113, P114, P115, P116, . . . , P117, P118, and P119 corresponds.
The sustaining period 104 is a period during which sustaining discharge to cause the display cell 131 for which writing discharge was made to occur to emit light in a manner to correspond to video data is made to occur between the scanning electrode 122-i and the sustaining electrode 123-i, to which timing P119 and P120 corresponds.
The initializing period 102 includes a sustaining erasing period 108, a priming period 109, and a priming erasing period 110. The sustaining erasing period 108 is a period during which wall charges having been accumulated between the scanning electrode 122-i and the sustaining electrode 123-i when sustaining discharge occurred during the sustaining period 104 are erased (initialized or reset), to which the timing P106, P107, P108 and P109 corresponds. The priming period 109 is a period during which priming effect is made to be produced, to which the timing P109, P110 and P111 corresponds. The priming erasing period 110 is a period during which wall charges having been accumulated on the dielectric layer in each of the display cells 131 as a result of the priming effect are erased, to which the timing P111, P112 and P113 corresponds.
Driving waveforms applied during the sustaining period in a pre-subfield 101 existing before the sub-field 105 are described. A sustaining voltage Vs and a ground voltage GND being lower than the sustaining voltage Vs are alternately applied as a sustaining pulse to the sustaining electrode 123-1 to 123-m and a ground voltage GND and the sustaining voltage Vs are alternately applied to the scanning electrodes 122-1 to 122-m by the driving control circuit 138. By the driving control circuit 138, a ground voltage GND is applied to the data electrodes 129-1 to 129-n. At the timing P101 immediately before the initializing period 102, by the driving control circuit 138, a ground voltage GND is applied to the scanning electrodes 122-1 to 122-m and a sustaining voltage Vs is applied by the driving control circuit 138 to the sustaining electrodes 123-1 to 123-m.
Driving waveforms (ramp waveforms of voltages to be applied to electrodes during the sustaining erasing period 108) applied during the sustaining erasing period 108 in the initializing period 102 are described. For a period from the timing P106 to the timing P107, the sustaining voltage Vs having been applied to the scanning electrodes 122-1 to 122-m is held by the driving control circuit 138. During a period from the timing P107 to the timing P108, a voltage to be applied to the scanning electrodes 122-1 to 122-m is lowered gradually from the sustaining voltage Vs to a ground voltage GND by the driving control circuit 138. For a period from the timing P108 to the timing P109, the ground voltage GND having been applied to the scanning electrodes 122-1 to 122-m is held by the driving control circuit 138. At the timing P106, a sustaining voltage Vs is applied to the sustaining electrodes 123-1 to 123-m by the driving control circuit 138. For a period from the timing P106 to the timing P109, the sustaining voltage Vs having been applied to the sustaining electrodes 123-1 to 123-m is held by the driving control circuit 138. The sustaining voltage Vs is about 170 V. For a period from the timing P106 to the timing P109, the ground voltage GND having been applied to the data electrodes 129-1 to 129-n is held by the driving control circuit 138.
Driving waveforms (priming waveforms being ramp waveforms of voltages to be applied to electrodes during the priming period 109) applied during the priming period 109 in the initializing period 102 are described. At the timing P109, a sustaining voltage VS is applied to the scanning electrodes 122-1 to 122-m by the driving control circuit 138. Next, during a period from the timing P109 to the timing P110, the sustaining voltage Vs having been applied to the scanning electrodes 122-1 to 122-m is gradually boosted to a priming voltage Vp by the driving control circuit 138. The priming voltage Vp is higher than the sustaining voltage Vs and its crest value is about 380 V to 450 V. Next, for a period from the timing P110 to the timing P111, the priming voltage Vp having been applied to the scanning electrodes 122-1 to 122-m is held by the driving control circuit 138. During a period from the timing P109 to the timing P111, a ground voltage GND is applied to the sustaining electrodes 123-1 to 123-m by the driving control circuit 138. For a period from the timing 109 to the timing P111, the ground voltage GND having been applied to the data electrodes 129-1 to 129-n is held by the driving control circuit 138.
Driving waveforms (ramp waveforms being waveforms of voltages to be applied to electrodes during the priming erasing period 110) applied during the priming erasing period 110 in the initializing period 102 are described. At the timing P111, a voltage to be applied to the scanning electrodes 122-1 to 122-m is lowered from the priming voltage Vp to the sustaining voltage Vs by the driving control circuit 138. Next, during a period from the timing P111 to the timing P112, a voltage to be applied to the scanning electrodes 122-1 to 122-m is lowered from the sustaining voltage Vs to a ground voltage GND by the driving control circuit 138. Then, for a period from the timing P112 to the timing P113, the ground voltage GND having been applied to the scanning electrodes 122-1 to 122-m is held by the driving control circuit 138. At the timing P111, a sustaining voltage Vs is applied to the sustaining electrodes 123-1 to 123-m by the driving control circuit 138. Next, for a period from the timing P111 to the timing P113, the sustaining voltage Vs having been applied to the sustaining electrodes 123-1 to 123-m is held by the driving control circuit 138. During a period from the timing P111 to the timing P113, a ground voltage GND is applied to the data electrodes 129-1 to 129-n by the driving control circuit 138.
Driving waveforms applied during the scanning period 103 are described. For a period from the timing P113 to the timing P119, the sustaining voltage Vs having been applied to the sustaining electrodes 123-1 to 123-m is held by the driving control circuit 138. At the timing P113, a scanning base voltage Vbw is applied to the scanning electrodes 122-1 to 122-m by the driving control circuit 138. Next, for a period from the timing P113 to the timing P119, the scanning base voltage Vbw having been applied to the scanning electrodes 122-1 to 122-m is held by the driving control circuit 138. A lowest value of the scanning base voltage Vbw is a ground voltage GND being a reference voltage and its peak value is set to be lower than the sustaining voltage Vs, which is about 80 to 110 V. Next, while the scanning base voltage Vbw is being applied to the scanning electrodes 122-1 to 122-m, a scanning pulse potential 111 to counter the scanning base voltage Vbw is applied to the scanning electrodes 122-1 to 122-m by the driving control circuit 138 sequentially at the timing P114, P115, P116, . . . , and P117. The scanning pulse potential 111 is a pulse having a negative polarity which lowers from a set value being a highest value of the scanning base voltage Vbw to a ground voltage GND being a lowest value of the scanning base voltage Vbw. That is, when the scanning pulse potential 111 is applied to the scanning electrodes 122-1 during a period from the timing 114 to the timing P115 and to the scanning electrodes 122-2 during a period from the timing P115 to the timing P116, and to the scanning electrode 122-m during a period from the timing P117 to the timing P118, the scanning base voltage Vbw is not applied to the scanning electrodes 122-1 during a period from the timing P114 to the timing P115 and is not applied to the scanning electrode 122-2 during a period from the timing P115 to the timing P116 and is not applied to the scanning electrode 122-m during a period from the timing P117 to the timing P118. When the scanning pulse potential 111 is applied to the scanning electrodes 122-1 to 122-m, a data pulse potential 112 corresponding to video data (display pattern) is applied to the data electrodes 129-1 to 129-n by the driving control circuit 138.
Driving waveforms applied during the sustaining period are described. A sustaining voltage Vs is applied, as a primary sustaining pulse potential serving as a sustaining pulse potential, to the scanning electrodes 122-1 to 122-m by the driving control circuit 138 and a ground voltage GND is applied, as the primary sustaining pulse potential serving as the sustaining pulse potential to the sustaining electrodes 123-1 to 123-m by the driving control circuit 138. Thereafter, until the timing P120, the sustaining voltage Vs and ground voltage GND are alternately applied as the sustaining pulse potential to the scanning electrodes 122-1 to 122-m by the driving control circuit 138 and the ground voltage GND and sustaining voltage Vs are alternately applied as the sustaining voltage to the sustaining electrodes 123-1 to 123-m. During a period from the timing P119 to the timing P120, a ground voltage GND is applied to the data electrodes 129-1 to 129-n by the driving control circuit 138.
Next, roles of each of the periods for driving the conventional plasma display device are described.
First, roles of the initializing period 102 are explained. Before the initializing period, the sustaining period in the pre-subfield 101 exists. Depending on whether or not sustaining discharge occurs in the pre-subfield 101, an amount of formation of wall charges that are accumulated on the dielectric layers (transparent dielectric layer 124 formed on the scanning electrode 122-i, transparent dielectric layer 124 formed on the sustaining electrode 123-i, and the white dielectric layer 128 formed on the data electrode 129-j) formed on each of the electrodes in the display cell 131, by discharge, varies. If subsequent writing discharge is made to occur despite the above state, due to influences exerted by different amounts of formation of the wall charges, it is difficult to make writing discharge occur correctly and/or writing discharge is caused to erroneously occur with timing with which writing discharge should not occur. During the sustaining period, discharge intensity is great. Because of this, if sustaining discharge occurs, a large amount of space charges are generated in the discharge space 126. The space charges are attracted by an electric field in the display cell 131 and are accumulated on the dielectric layer on each of the electrodes. Since the amount of the space charges is large, wall charges are accumulated on each of the electrodes in the display cell 131 so that the electric field in the display cell 131 becomes zero. At this point, wall charges accumulated on each of the electrodes, at the timing P101, is put into such a state (arrangement of charges) as shown in FIG. 20A, and positive wall charges (+e) are accumulated on all the sustaining electrode 123-i and data electrode 129-i and negative wall charges (−e) are accumulated on all the scanning electrode 122-i. By the formation of the above wall charges, wall voltages (voltages produced by the wall charges between the electrode and dielectric layer) being almost equal to the sustaining voltage Vs are formed between the scanning electrode 122-i and sustaining electrode 123-i (that is, in the discharge gap 134).
Roles of the initializing period 102 are:    (1) to erase (initialize or reset) wall charges accumulated on the dielectric layer in each of the display cells 131 in a light emitting state during the sustaining period in the pre-subfield 101, and    (2) to cause priming effects to occur in order to achieve easy occurrence of writing discharge when video data is written in a pixel (display cell 131) during the scanning period 103. In the first role above, by erasing (initializing or resetting) wall charges, a pixel (display cell 131) is forcedly discharged. During the initializing period 102, the above first role (1) is performed during the sustaining erasing period 108 and the above second role (2) is performed during the priming period 109 and the priming erasing period 110. During the sustaining erasing 108, discharge occurs only when sustaining discharge had occurred in the pre-subfield 101. During the priming period 109 and priming erasing period 110, discharge occurs irrespective of whether or not sustaining discharge had occurred in the pre-subfield 101.
Next, roles of the sustaining erasing period 108, priming period 109, and priming erasing period 110 are described. When the period is shifted from its sustaining period in the pre-subfield 101 to its sustaining erasing period 108, a difference in potential in the discharge space 126 between the scanning electrode 122-i and sustaining electrode 123-i gradually increases and weak discharge called “feeble discharge” occurs in a sustained manner. Discharge intensity of the feeble discharge is low. Due to this, feeble discharge occurs only in the vicinity of the discharge gap 134. At this point, wall charges accumulated in a portion being in the vicinity of the discharge gap 134 on the scanning electrode 122-i and on the sustaining electrode 123-i decrease and wall charges accumulated on each electrode are put into such a state (arrangements of wall charges) as shown in FIG. 20B. That is, negative wall charges (−e) in the portion being in the vicinity of the discharge gap 134 on the scanning electrode 122-i and positive wall charges (+e) in the portion being in the vicinity of the discharge gap 134 on the sustaining electrode 123-i decrease and negative wall charges (−e) are accumulated in the portion being in the vicinity of the discharge gap 134 on the sustaining electrode 123-i.
When the period is shifted from its sustaining erasing period 108 to its priming period 109, in addition to the feeble discharge occurring between the scanning electrode 122-i and sustaining electrode 123-i, feeble discharge also occurs between the scanning electrode 122-i and data electrode 129-i. At this time, wall charges are accumulated by the feeble discharge in the portion being in the vicinity of the discharge gap 134 on the scanning electrode 122-i, sustaining electrode 123-i, and data electrode 129-j and wall charges accumulated on each electrode is put into such a state (arrangements of wall charges) as shown in FIG. 20C. That is, negative wall charges (−e) are further accumulated in the portion being in the vicinity of the discharge gap 134 on the scanning electrode 122-i and positive wall charges (+e) are further accumulated in the portion being in the vicinity of the discharge gap 134 on the sustaining electrode 123-i and positive charges (+e) are further accumulated in the portion being in the vicinity of the discharge gap 134 on the data electrode 129-j and on a surface facing the scanning electrode 122-i.
When the period is shifted from its priming period 109 to its priming erasing period 110, feeble discharge occurs in the vicinity of the discharge gap 134. At this time, during the priming period 109, wall charges accumulated in the portion being in the vicinity of the discharge gap 134 on the scanning electrode 122-i, sustaining electrode 123-i, and data electrode 129-j decrease and wall charges accumulated on each electrode is, at timing of the P112, put into such a state (arrangements of wall charges) as shown in FIG. 2D. That is, negative wall charges (−e) accumulated in the portion being in the vicinity of the discharge gap 134 on the scanning electrode 122-i, positive wall charges (+e) accumulated in the portion being in the vicinity of the discharge gap 134 on the sustaining electrode 123-i, and positive wall charges (+e) accumulated in the portion being in the vicinity of the discharge gap 134 on the data electrode 129-j decrease and negative wall charges (−e) are accumulated in the portion being in the vicinity of the discharge gap 134 on the sustaining electrode 123-i.
Next, roles of the scanning period are described. The driving control circuit 138, during the scanning period 103, in order to write video data in an address (display cell 131) by causing writing discharge to occur between the scanning electrode 122-i and data electrode 129-j, when applying a scanning pulse potential 111 sequentially to the scanning electrodes 122-1 to 122-m, applies a data pulse potential 112 corresponding to the video data (display pattern) to the data electrodes 129-1 to 129-n. At this time, wall charges accumulated on each electrode is put into such a state (arrangements of wall charges) as shown in FIG. 2E. That is, negative wall charges (−e) accumulated on the scanning electrode 122-i, positive wall charges (+e) accumulated on the sustaining electrode 123-i, and positive wall charges (+e) accumulated on the data electrode 129-j decrease and positive wall charges (+e) are accumulated on all portions on the scanning electrode 122-i and negative wall charges (−e) are accumulated on all portions on the sustaining electrode 123-i.
In a pixel (here, display cell 131) in which the data pulse potential 112 has been applied to the data electrodes 129-1 to 129-n, wall voltages are superimposed on voltages existing in the discharge space 126 between the scanning electrode 122-i and data electrode 129-j and, as a result, a voltage exceeding a discharge initiating voltage is applied between the scanning electrode 122-i and data electrode 129-j. Due to this, writing discharge occurs between the scanning electrode 122-i and data electrode 129-j. A difference in potential between the scanning electrode 122-i and sustaining electrode 123-i appearing when the writing discharge occurs is “Vs”. When such the potential difference occurs, if writing discharge occurs between the scanning electrode 122-i and data electrode 129-j, surface discharge is induced between the scanning electrode 122-i and sustaining electrode 123-i. At this time, negative wall charges (−e) are accumulated on the sustaining electrode 123-i, positive wall charges (+e) are accumulated on the scanning electrode 122-i, and a state in which wall charges are accumulated on each electrode in a manner as shown in FIG. 20D is changed, at the timing P119, to be such a state (arrangements of wall charges) as shown in FIG. 20E. On the other hand, in a pixel (here, display cell 131) in which a data pulse potential 112 is not applied to the data electrodes 129-1 to 129-n, since a discharge initiating voltage is not exceeded, no writing discharge occurs and wall charges still remains in such a state as shown in FIG. 20D. Thus, depending on absence or presence of the data pulse potential 112 being applied to the data electrodes 129-1 to 129-n, two kinds of states of wall charges can be brought about.
Next, roles of the sustaining period 104 are described. When application of the scanning pulse potential 111 to all lines of the electrodes (scanning electrodes 122-1 to 122-m) has been completed, since the driving control circuit 138 makes sustaining discharge occur that causes the display cell 131 in which writing discharge occurred to emit light in a manner to correspond to video data between the scanning electrode 122-i and sustaining electrode 123-i, the period is shifted from its scanning period 103 to its sustaining period 104. A sustaining voltage Vs is applied, as a sustaining pulse potential, alternately to the scanning electrodes 122-1 to 122-m and sustaining electrodes 123-1 to 123-m. The sustaining voltage Vs (sustaining pulse potential), in a pixel (display cell 131) in which no writing discharge occurs, is set to be a voltage at which discharge (surface discharge) between the scanning electrode 122-i and sustaining electrode 123-i is not initiated.
In a pixel (display cell 131) in which writing discharge occurred, positive wall charges (+e) are accumulated on the scanning electrode 122-i and negative wall charges (−e) are accumulated on the sustaining electrode 123-i. Due to this, these positive and negative wall voltages are superimposed on a first sustaining pulse potential (being called a “first sustaining pulse potential”) to be applied to the scanning electrode 122-i. At this time, a voltage exceeding a discharge initiating voltages is applied to the discharge space 126, causing sustaining discharge to occur. By this sustaining discharge, negative wall charges are accumulated on the scanning electrode 122-i and positive wall charges are accumulated on the sustaining electrode 123-i. The wall voltages are superimposed on a subsequent sustaining pulse potential (being called a “second sustaining pulse potential”) to be applied to the sustaining electrode 123-i. At this time, a voltage exceeding the discharge initiating voltage is applied to the discharge space 126, causing sustaining discharge to occur. By this sustaining discharge, a wall charge of a polarity opposite to the first sustaining pulse potential is accumulated on the scanning electrode 122-i and sustaining electrode 123-i. That is, positive wall charges are accumulated on the scanning electrode 122-i and negative wall charges are accumulated on the sustaining electrode 123-i. Since a sustaining voltage Vs (sustaining pulse potential) continues to be applied alternately to the scanning electrode 122-1 to 122-m and sustaining electrode 123-1 to 123-m for a period until the sustaining period 104 terminates, the sustaining discharge occurs in a sustained manner. During the sustaining period 104, a potential difference produced by wall charges that occurred by the x-th (x=1, 2, 3, . . . ) time sustaining discharge is superimposed on the (x+1) th time sustaining pulse, thus causing the sustaining discharge to occur in a sustained manner. Light emitting luminance is determined according to the number of times of sustaining discharge.
Thus, the initializing period 102, scanning period 103, and sustaining period 104 are collectively called a “sub-field” 105. When gray-level display is performed, one field during which one screen of image information is displayed is made up of a plurality of the sub-fields 105. The gray-level display is made possible by changing the number of potentials of the sustaining pulse in each of the sub-fields 105 and by causing a display cell to emit light or not in each of the sub-fields 105.
However, in the conventional plasma display device using the conventional three-electrode AC-type PDP and in the conventional method for driving the same, when a data pulse potential 112 is low and/or a pulse width of the data pulse potential 112 is short, surface discharge cannot be satisfactorily induced. In this case, unless sufficient negative wall charges (−e) are accumulated on the sustaining electrode 123-i, even if writing discharge occurs, sustaining discharge does not occur during the sustaining period 104, thus causing erroneous discharge (erroneous lighting-off). When the first sustaining pulse potential is applied to the scanning electrode 122-i, since a voltage being applied to the scanning electrode 122-i becomes a sustaining voltage Vs and a voltage being applied to the sustaining electrode 123-i becomes a ground voltage GND, negative wall charges (−e) accumulated on the sustaining electrode 123-i play an important role in causing the sustaining discharge following the writing discharge to occur. In the conventional method described above, in a state before occurrence of the writing discharge, as shown in FIG. 20D, positive wall charges (+e) are accumulated on the sustaining electrode 123-i. Therefore, to reverse the positive wall charges (+e) accumulated on the sustaining electrode 123-i to be positive wall charges (−e) by writing discharge, much current is required.
In the conventional method for driving the conventional PDP, when writing discharge is made to occur, in addition to currents required for discharge between the scanning electrode 122-i and data electrode 129-j, currents required for discharge between the scanning electrode 122-i and sustaining electrode 123-i has to be flown through the scanning electrode 122-i. Due to this, when writing discharge occurs in all pixels (display cells 131) on one line, currents (writing current) required for causing writing discharge to occur is about 500 mA to 700 mA at its peak value in the case of a 42-inch panel, which flow through the scanning electrodes 122-1 to 122-m (one line). Especially, when a peak value of a required writing current is larger than a reference value, due to high resistance occurring when the scanning electrodes 122-1 to 122-m are wired and/or voltage drop that occurs when current supplying capability of the scanning driver is small, voltages being applied to the scanning electrode 122-i and data electrode 129-j decrease.
Therefore, since the voltage being applied to the scanning electrode 122-i and data electrode 129-j decreases, unless a data pulse potential being higher than the data pulse potential 112 is applied, normal writing discharge does not occur anymore. Thus, in the conventional method, due to display load (scanning electrode wring resistance) in a direction (row direction) from the scanning electrode 122-1 to the scanning electrode 122-m, in some cases, normal writing discharge does not occur.
To solve this problem, methods are available in which a data pulse potential is set to be higher than the data pulse potential 112 used in the conventional method, a scanning electrode wiring resistance is set to be lower than the scanning electrode wiring resistance used in the conventional method, a current supply capability of a scanning driver is higher than the current supply capability used in the conventional method, or a like. However, if the data pulse potential is set to be higher than that employed in the conventional method and if the current supply capability of the scanning driver is set to be higher than that employed in the conventional method, costs for driving a plasma display device become higher than that for driving conventional plasma display device. Moreover, in order to make the scanning electrode wiring resistance be lower than that employed in the conventional method, if a thickness of a film of the scanning electrode 122-i is increased, costs for electrode materials used to increase its film thickness and for compensating for a drop in a throughput become higher compared with the case of the conventional method for driving the conventional PDP.
Patent references cited in the above description include the followings:    1. Japanese Patent Application Laid-open No. 2001-350445    2. Japanese Patent Application Laid-open No. 2001-296834    3. Japanese Patent Application Laid-open No. 2000-231361    4. Japanese Patent Application Laid-open No. 2000-206933    5. Japanese Patent Application Laid-open No. 2000-214822    6. Japanese Patent Application Laid-open No. 2001-134232    7. Japanese Patent Application Laid-open No. 2001-184021    8. Japanese Patent Application Laid-open No. 2001-272946    9. Japanese Patent Application Laid-open No. 2002-132207    10. Japanese Patent Application Laid-open No. Hei 10-105111    11. Japanese Patent Application Laid-open No. 2001-184023    12. Japanese Patent Application Laid-open No. 2001-228820    13. Japanese Patent Application Laid-open No. 2002-229508    14. Japanese Patent Application Laid-open No. Hei 11-024626    15. Japanese Patent Application Laid-open No. Hei 11-327505